1. Field of the Invention
The present invention is related to a gate driver, and more particularly, to a gate driver with a start protection circuit.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a diagram illustrating the conventional Liquid Crystal Display (LCD) device. The conventional LCD device 10 comprises a system board 12 and a display panel 16. A power source circuit 14 is disposed on the system board 12. A gate driver 18 is disposed on the display panel 16. The gate driver 18 comprises a shift register 181, a level shifter 182 and an output buffer 183. The shift register 181 receives the control signals CPV, UD, XON, OE and STV of the LCD device 10. The level shifter 182 receives the gate low voltage VEEG and the gate high voltage VDDG generated from the power source circuit, for accordingly generating the gate control signal VG. The output buffer 183 outputs the gate control signal VG to the display panel 16. The power source circuit 14 is utilized to generate the operational voltages required for the LCD device 10. The power source circuit 14 comprises a DC/DC converter 141, a charge pump 142, a first delay unit 143 and a second delay unit 144. The DC/DC converter 141 converts the power source voltage VCC to the voltage VDDA. The charge pump 142 generates the gate low voltage VEEG and the gate high voltage VDDG according to the voltage VDDA.
Please refer to FIG. 2. FIG. 2 is a timing diagram illustrating the correct power on sequence of the operational voltages when the conventional gate driver is turned on. When the LCD device 10 is booted up, the power source voltage VCC reaches a stable voltage level, then the gate low voltage VEEG reaches a low voltage level for the gate driver 18 to turn off all the scan lines to prevent the boot up noise. Afterwards the gate high voltage is activated to reach a high voltage level for driving the scan lines. Therefore, for the LCD device 10 to function properly and for preventing causing damages to the gate driver 18, the correct power on sequence of the operational voltages of the LCD device 10 is as below:
VCC->VEEG->VDDG
According to the above power on sequence, the gate low voltage VEEG and the gate high voltage VDDG are passed through the first delay unit 143 and the second delay unit 144 respectively before being transmitted to the level shifter 182, so the gate low voltage VEEG is transmitted to the gate driver 18 prior to the gate high voltage VDDG. Thus, the correct power on sequence is attained.
Please refer to FIG. 3. FIG. 3 is a timing diagram illustrating the incorrect power on sequence of the operational voltages when the conventional gate driver is turned on. Normally the gate low voltage VEEG is activated prior to the gate high voltage VDDG, for the gate driver 18 to turn off the entire scan lines; this way abnormal behaviors caused by the incorrect power on sequence when the LCD device 10 is booted up can be prevented. However, since the gate driver 18 of the conventional LCD 10 does not incorporate any detection mechanisms for monitoring the power on sequence of the operational voltages, the occurrence of incorrect power on sequence and the relative consequences cannot be effectively prevented. For instances, at the instance of when the LCD device 10 is booted up, the power source circuit 14 may transmit the gate low voltage VDDG and the gate high voltage VEEG synchronously (i.e. at the same time) to the display panel 16, the gate low voltage VEEG is likely to generate spikes due to the coupling effect of the gate high voltage VDDG, causing the gate driver 18 to function improperly. Consequently the LCD device 10 may not be able to boot up, or even the gate driver 18 may be damaged.